Petrovic M.Milovanović, Vladimir2022-02-022022-02-022021https://scidar.kg.ac.rs/handle/123456789/14007Fully streaming linear sorters with their rather simple and low-cost hardware architecture are widely used as the fundamental building blocks in many digital signal processing applications that require sorting operations and continuous data streaming interfaces. Therefore, a parameterizable and runtime reconfigurable generator of fully streaming sorters based on an insertion sort algorithm are captured inside Chisel hardware design language in order to enable fast and efficient agile design space exploration. A broad range of parameter settings are supported with the proposed generator, such as sorting data type and data width in number of bits, discarding element position inside the sorting array, compile and runtime reconfigurable sorter depth, sorting direction, control and status register access bus, etc. Various generator instances have been mapped onto a commercially available FPGA platform, tested and mutually compared. It is proven that such a generator can yield resource and performance competitive sorter designs.restrictedAccessconferenceObject10.1109/MIEL52794.2021.95691532-s2.0-85118424351